The present invention relates to an apparatus and a method for compensating the voltage error caused by dead time of switching elements which are used in electronic appliances such as converters, inverters or motors, and more particularly to an apparatus and a method for compensating the voltage error and the output current distortion caused by dead time of switching elements in a PWM converter or PWM inverter.
FIG. 1 illustrates a circuit configuration of an inverter which is constituted by semiconductor switching elements. More specially, the inverter is formed by phase bridges which are constituted by series-connecting one switching element in parallel with a reverse recovery diode and another switching element in parallel with another reverse recovery diode. The load is connected to the node of the series connection which defines the output terminal of the inverter.
It is well known that a typical semiconductor switching element has an intrinsic delay time interval from the receipt of an on or off gate drive signal to the starting up of its switching action. The action of the switching element is turning on normally faster than turning off. Also, the duration of action of a gate drive circuit depends on its characteristics. Accordingly, if one of the two switching elements in the upper or lower arm of a phase bridge is turned off and the other switching element is turned on without giving a delay simultaneously, a short circuit may be produced. To prevent the short circuit of the power supply in pulse width modulated (PWM) voltage inverters or converters, the gate drive signal is preset with a dead time which is determined under the consideration of differences between the delays that are intrinsic to the elements and circuits. Therefore, the dead time is necessary to prevent the short circuit of the power supply in pulse width modulated (PWM) voltage inverters or converters resulting in output deviations. Although individually small, when accumulated over an operating cycle, the voltage deviations are sufficient to distort the applied PWM signal.
Actually, the dead time causes an error voltage between the command voltage and the actual output voltage, thereby resulting in disadvantages such as current distortion and torque ripple. For simplicity, the effects of dead time can best be examined from one phase of an inverter, e.g. phase U.
Referring to FIGS. 1 and 2, PWMu is the PWM command signal without the dead time. PWM1 and PWM4 are the actual gate driver signals of switching elements T1 and T4 with the dead time Td inserted respectively. The inverter output voltage UUO is the voltage of U-phase output with reference to the neutral xe2x80x98Oxe2x80x99 which is an imaginary mid-point of the DC bus. The positive direction of phase currents is defined in FIGS. 1 and 2. Assuming iu greater than 0, after PWM1 resets, in the period of dead time, both T1 and T4 are non-conductive. However, due to the inductive load, the output current is continuous. It then flows through the freewheeling diode D4 and the negative DC bus voltage is connected to the output. So the terminal U has substantially the same potential as the negative terminal of the DC bus. Likewise, when the output current iu is flowing into the inverter, i.e. iu less than 0, after PWM4 resets, in the period of dead time, the output current flows through the freewheeling diode D1 and the terminal presents the positive voltage. It can be thus known that the output voltage is determined by the direction of the output current rather than the control signals of the switching elements during the dead time period.
The Uerror, as shown in FIG. 2, illustrates these resultant deviation voltage pulses caused by the dead time. Assuming the switching elements are ideal, that is, both voltage drop and switching times are neglected, all these deviation pulses have the same height of Ud and the same width of Td. These deviation voltage pulses due to dead time are opposite to the current in either direction. As a result, the output current magnitude is reduced, regardless of its polarity.
Many industrial approaches for compensating this inevitable dead time have been suggested in PWM techniques. Most of them are based on the average value theory in which the error is averaged over an operating cycle and then added to a command voltage. Contrarily, the pulse based consideration in the dead time compensation method is also suited. Those pulsed-based methods provide more accurate compensation but increase the burden of the processor.
A conventional dead time compensation method will be described with reference to FIG. 3. FIG. 3 shows a flowchart for calculating a compensating voltage Vcomp so as to compensate the deviation voltage in accordance with the dead time. A current detector detects (Step S1) the output current iu and the controller judges (Step S2) the polarity of the detected current iu. Here, if the value of the detected current is positive, a compensating voltage Vcomp for compensating the voltage error according to dead time is set as a predetermined positive value (Step S3). If the value of the detected current remains negative, the compensation voltage Vcomp is set (step S4) as a predetermined negative value. Next, by adding the compensation voltage Vcomp to a command voltage Vcmd, there is obtained (Step S5) a new compensation voltage Vxe2x80x2cmd.
Whereas, when the polarity of the current iu is judged as negative, the command voltage Vxe2x80x2cmd is obtained by subtracting the dead time compensating voltage Vcomp of the inverter. When the polarity of the current iu is judged as positive, the command voltage Vxe2x80x2cmd is obtained by adding the dead time compensating voltage Vcomp of the inverter.
However, as the current magnitude is small around current zero crossing point (ZCP), the noise and the transient caused by the PWM signal are added onto the little current signal. This makes it difficult for the current detector to detect current direction precisely, and the dead time compensation voltage is not in step with the actual current direction. As a result, the current distortion becomes worse.
As aforementioned, the dead time effects are analyzed on the assumption that the delay time of the switching elements is neglected. This assumption is reasonable when the output current is large but not the case that the output current is small especially around ZCP. FIG. 4 illustrates the effect of turning off time of switching elements on the output voltage, where part a) is the ideal PWM signal without dead time inserted, and part b) and c) are the actual PWM signal with the dead time inserted corresponding to the upper and lower switching elements respectively. Td means the inserted dead time. The bold solid line in part d) presents the case of the high positive output current, and the dashed line presents the case of the low positive output current. For the high positive current, the induction of motor quickly drives Uuo to a low voltage during the dead time interval. However for a low positive current, during the dead time interval, the inductance of the motor has difficulty to reduce Uuo due to the interaction with the large Toff as well as the parasitic inductance and the capacitance of the system. Thus the high voltage Uuo decays slowly during the dead time interval. Consequently, the above foresaid deviation voltage pulses come to be shortened. As a result, the voltage error caused by the dead time is lightened, and in another word, the dead time is partly compensated automatically. When the positive current is small enough, Uuo may come to its utmost which is illustrated as the highest dashed line in part d) and the above foresaid deviation voltage pulses will be zero. As a result, the width of the output voltage Uuo equals to that of the ideal command PWM which is clearly illustrated in parts a) and d) Ta=Tb. This means that dead time is fully compensated automatically. Likewise for a negative current, Uuo increasing slowly as the dashed line illustrated in part e) and the deviation voltage caused by dead time reduces gradually as current decreasing.
The above analysis is based on the assumption that the output current does not change its direction in one PWM cycle. Actually, there is similar phenomenon as the current direction continually alternates in one or more sequential PWM cycles, which is called multi-ZCP. There are several situations of multi-ZCP. For simplicity, only the typical one is described as following.
As illustrated in FIG. 5, the output current is small. Accordingly, Toff is large and cannot be neglected. Like the process described above, in the interval labeled as Tx, from the instant of PWM1 falling, the output voltage Uuo slowly goes to a low level as the dashed line illustrated. With the decreasing of the output current, Uuo will go along the upper dashed line, and may reach the utmost as the level dashed line. Similar operations are performed when in the next dead time labeled as Ty. The average width of Uuo can be illustrated as Tb. Hence Ta=Tb, that is to say, the width of the output voltage Uuo equals to that of the ideal command PWM. Accordingly, the dead time is compensated automatically.
It can be seen that in one output current cycle, the deviation voltage is not of the same effect. When the output current is large, the deviation caused by dead time is relatively large, and when the output current is small, the deviation caused by dead time is relatively small. The current flatter around current zero point, which is illustrated in FIG. 6, is just caused by this deviation voltage.
It is therefore attempted by the applicant to deal with the above situation encountered with the prior art.
It is therefore an object of this invention to propose a dead time compensation method, in which the compensation voltage is relative to the current distortion by applying a bias current. This adaptive compensation voltage is added onto the command voltage by adjusting PWM duty according to the current phase angle. As a result, the current distortion is compensated in feedback and presents good performance and high robustness.
It is therefore another object of this invention to propose an apparatus and a method for compensating dead time effects in inverters or converters having one or more legs with two complementary switches. The method of the invention mainly includes the following steps providing a pulse width modulation (PWM) reference, detecting the crossing points of the output current through a predetermined bias value, providing a dead time compensation signal which is adjusted in response to the crossing points, and adding the dead time compensation signal to the PWM reference. Hence an adaptive compensation is accomplished independent of types of switching elements and load conditions. A high reliable circuit with low cost can be provided as a preferred embodiment of bias current crossing points detection.
In this invention, the presented compensation method is intentionally features the following aspects. The bias current crossing points are detected instead of zero crossing points of the output current as in the prior all. The point in time of the polarity change in the dead time compensation signal is auto-adjusted in response to the detected bias current crossing points and is essentially asynchronous with reference to zero crossing points of the output current feedback or the output current reference. The dead time compensation signal is adjusted instantly in response to the detected bias current crossing points and the shape of it deviates from original compensation signal. The shape of the original compensation signal is an approximately periodical waveform of broken line with a gap around the zero crossing point of the output current. The point in time of the polarity change in the dead time compensation signal is in advance of that of the output current. The compensation signal is continuously varied from negative to positive or vice versa, while the slope ratio may be altered instantly in response to the detected bias current crossing points. The bias current crossing point is detected in the following steps: injecting a bias current from a simple circuit into the output terminal during the interval that the output terminal is connected to ground of DC bus, sampling the terminal voltage during this interval, and comparing the sampled voltage to a predetermined value. Finally, the point in time of logic level change in the comparison output signal indicates the bias current crossing point.
According to the aspect of the present invention, the method for compensating a dead time effect in an electronic appliance, includes the steps of: providing a pulse width modulation (PWM) reference, providing a first dead time compensation signal based on the pulse width modulation reference, detecting a bias current crossing point that is an output current passing through a predetermined bias level, generating a second dead time compensation signal instead of the first dead time compensation signal instantly in response to the detected bias current crossing point, and adding the second dead time compensation signal to the pulse width modulation reference.
Certainly, the electronic appliance is selected from the group consisting of an inverter and a converter.
Certainly, the dead time effect is selected from the group consisting of an output voltage error and a current distortion.
Preferably, a crossing point of polarity change in the second dead time compensation signal is auto-adjusted in response to the bias current crossing point and shifted in accordance with a near zero crossing point of an output current unless the system comes into a steady state.
Preferably, a shape of the second dead time compensation signal is auto-adjusted in response to the bias current crossing point and deviated from the first dead time compensation signal unless the system comes into a steady state.
Preferably, either the first dead time compensation signal or the second dead time compensation signal is continuously varied from negative to positive or vice versa, while the slope ratio is altered instantly in response to the bias current crossing point unless the system comes into a steady state.
Preferably, the crossing point of polarity change in either the first dead time compensation signal or the second dead time compensation signal is shifted in time in accordance with a near zero crossing point of an output current.
Preferably, the shape of first dead time compensation signal is an approximately periodical waveform of broken line with a gap near a zero crossing point of an output current.
Preferably, the step of detecting the bias current crossing point further includes the following steps of injecting a bias current into an output terminal of an inverter/a converter during a interval, sampling a terminal voltage during the interval, and comparing the sampled voltage to a predetermined value to obtain a comparison output signal, wherein a point in time, logic level change of the comparison output signal, indicates the bias current crossing point.
Certainly, the bias current can be in a positive direction or in a negative direction.
Preferably, a simple circuit being employed for detecting bias current crossing point includes a diode with its cathode end connected to the output terminal of a leg in one of an inverter and a converter, a resistor with one end connected to an anode end of the diode and the other end connected to a DC power source, wherein the value of the resistor equals to the result of dividing an amplitude of the DC power source by a value of the predetermined bias current, a comparator with one of its input ends connected to the anode end of the diode and the other input end connected to a predetermined potential, and a sampler with its input end connected to an output end of the comparator, wherein a sampling action is enabled during a interval that the output terminal of an inverter/a converter is connected to a ground of a DC bus therein.
Preferably, the step of adjusting the first dead time compensation signal further includes the following steps of detecting the initial output current direction signal, recording a period of the output current being positive or negative, and the output current cycle, calculating the average between the period of the output current being positive or negative, and extending a narrower period of the output current being positive or negative by a same width to its both sides, and compressing the wider period of the output current being positive or negative by the same width to its both sides for the purpose of making these two periods of the output current being substantially equal.
Preferably, the method of calculating the period of the current being positive or negative is carried out in terms of phase angle, or in terms of time.
The present invention may best be understood through the following description with reference to the accompanying drawings, in which: